1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device provided with an insulated gate field effect transistor used in an element for driving a microprocessor, a microcomputer, a semiconductor memory or a liquid crystal display, and a method of manufacturing the same.
2. Description of the Prior Art
Various research and development is being conducted with respect to achieving micronization and high integration of a semiconductor element.
In particular, the development of technique of micronizing an insulated gate field effect transistor called a Metal Insulator Semiconductor FET (MISFET) is remarkable. The micronization of a MISFET is achieved by shortening a length of a gate electrode in channel length direction. That the length of a gate electrode is shortened means naturally that the length of a channel region thereunder, i.e., the channel length is shortened. This fact means that the time required for carriers to pass through the channel region is reduced, thus resulting in a higher speed along with greater integration.
When the gate electrode is shortened, however, hot electrons are produced by a short channel effect, thus bringing about threshold voltage variation or lowering of channel conductance.
Namely, in a conventional structure a channel region composed of a first conductive type impurity diffused layer of low concentration is put between a source region and a drain region composed of a second conductive type impurity diffused layer of high concentration, an electric field applied to the vicinity of a boundary among a source region, a drain region and a channel region is increased in a state that voltage is applied between the source region and the drain region as the channel region is narrowed. As a result, the operation of a MISFET becomes very unstable.
A new structure of a MISFET that has been explicated for the purpose of controlling such a short channel effect is a structure of a Lightly Doped Drain (LDD). The LDD has a layer structure of a deep high impurity concentration region and a shallow low impurity concentration region formed in a source region and a drain region, and the low impurity concentration region of these regions stretches out a little toward the gate electrode. It has become possible to reduce the electric field produced in the vicinity of the boundary among the source region, the drain region and the channel region, thereby to stabilize the operation of the element by the LDD.
An example of a method of manufacturing a conventional insulated gate field effect transistor will be shown in FIGS. 1A to 1C.
First, as shown in FIG. 1A, a gate electrode 104 is formed through a gate oxide film 103 on a surface of a p-type semiconductor substrate 101 surrounded by a field insulating film 102. The gate oxide film 103 and the gate electrode 104 are formed through a film forming process and a photolithography process.
Then, n.sup.- type impurity diffused regions 105 and 106 having comparatively low impurity concentration are formed in a self-align manner by ion implantation using the gate electrode 104 and the field insulating film 102 as a mask.
Then, after an insulating film such as PSG and SiO.sub.2 are formed by chemical vapor deposition (CVD) on the whole body so as to cover the gate electrode 104 and the n.sup.- type impurity diffused regions 105 and 106, the insulating film is etched anisotropically in a perpendicular direction and made to remain locally on the side of the gate electrode 104 as shown in FIG. 1B. There is reactive ion etching (RIE) as anisotropic etching technique.
The remaining insulating film is called a spacer or a side wall in general. Further, n.sup.+ type impurity diffused regions 108 and 109 having high impurity concentration such as those shown in FIG. 1C are formed in a self-aligning manner by ion implantation for a second time using the gate electrode 104 and a side wall 107 as the mask.
Then, an interlayer insulating film 110 is formed on the whole body, and contact holes are formed therethrough, thereby to connect a source electrode 111 and a drain electrode 112 to the n.sup.+ type impurity diffused regions 108 and 109.
With this, an insulated gate field effect transistor having an LDD structure is formed in an element forming region.
A process of manufacturing an n-type MIS has been described above, but a p-type MIS is also formed through an almost similar process.
According to the process described above, however, since the side wall 107 on the side of the gate electrode 104 is formed by anisotropic etching, irradiation angles of ions used for etching become uneven and the width of the side wall 107 is dispersed when the substrate becomes large in size.
In a step of forming the side wall 107, since a process of depositing an insulating film in a reducing room is included, the processing speed drops and the period of time for etching the insulating film in a perpendicular direction further becomes necessary, which incur lowering of a throughput.
A semiconductor element having an LDD structure is formed on an insulative substrate such as a glass substrate and used as an active element of a liquid crystal display sometimes.
Since, the glass substrate used for the liquid crystal display has a tendency of forming a large area, a film thickness of an insulating film (such as PSG) forming the side wall is different depending on the location on the same substrate, and dispersion of the width of the side wall on the side of the gate electrode is increased. Further, the dispersion in the configuration of the side wall makes it difficult to control an impurity ion implantation quantity, therefore the characteristics of a thin film transistors formed on the same substrate are uneven.
There is a method of making an operation speed sufficiently high on condition that a short channel is made by making an aspect ratio higher by increasing the height of the gate electrode 104 so as to increase the sectional area of the gate electrode 104 and reducing the resistance of the gate electrode 104. The aspect ratio is a ratio of the height to the width (the width in the channel length direction).
In a conventional LDD, however, it has been impossible to increase the aspect ratio without restriction because of a problem in a manufacturing process. This is due to such a reason that the width of the side wall 107 formed by anisotropic etching depends on the height of the gate electrode 104. Normally, the width of the side wall 107 reaches 20% or more of the height of the gate electrode 104. When the width of the side wall 107 becomes wider, the n.sup.- type impurity diffused regions 105 and 106 become wider and the resistance between a source and a drain is increased, thus deteriorating transistor characteristics.